V23832-T2131-M101 Datasheet, PDF (6/30 Pages) Infineon Technologies AG – PAROLI 2 Tx AC, 1.6 Gbit/s

V23832-T2131-M101
V23832-R121-M101
Pin Configuration
Pin Description Receiver
Symbol Level/Logic Description
V_CC
V_CCO
REFR
Power supply voltage of pre amplifier and analog circuitry
Power supply voltage of output stages
LVDS = to be left open (t.b.l.o.)
V_EE
OEN
Ground
LVCMOS In
Output Enable High = normal operation.
Low = sets all Data Outputs to low.
This input has an internal pull-up which pulls to high level
when this input is left open.
ENSD
LVCMOS In
High = SD1 and –SD12 function enabled.
Low = SD1 and –SD12 are set to permanent active.
This input has an internal pull-up which pulls to high level
when this input is left open.
SD1
LVCMOS Signal Detect on fiber #1.
Out
High = signal of sufficient AC power is present on fiber #1.
Low = signal on fiber #1 is insufficient.
–SD12
LVCMOS
Out
low active
Signal Detect on fiber #12.
Low = signal of sufficient AC power is present on fiber #12.
High = signal on fiber #12 is insufficient.
DOxxP
LVDS Out Data Output #xx, non-inverted
DOxxN
LVDS Out Data Output #xx, inverted
t.b.l.o.
to be left open
Reserved
Reserved for future use
Data Sheet
6
2003-11-19