HYS72D32500GR-7F-B Datasheet, PDF (9/22 Pages) Infineon Technologies AG – Low Profile Registered DDR-I SDRAM-Modules

HYS 72Dxx5xxGR-7F/7/8-B
Registered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (-8: PC1600)
Symbol
Parameter/Condition
IDD0
Operating Current: one bank; active / precharge; tRC = tRC MIN; tCK = tCK
MIN; DQ, DM, and DQS inputs changing once per clock cycle; address and
control inputs changing once every two clock cycles
256MB
x72
1bank
-8
MAX
810
IDD1
Operating Current: one bank; active/read/precharge; Burst = 4;
900
Refer to the following page for detailed test conditions.
Precharge Power-Down Standby Current: all banks idle; power-down mode;
IDD2P
CKE <= VIL MAX; tCK = tCK MIN
63
Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle; CKE >=
IDD2F VIH MIN; tCK = tCK MIN ,address and other control inputs changing once per
315
clock cycle, VIN = VREF for DQ, DQS and DM.
Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle;
IDD2Q CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs stable at >=
198
VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM.
Active Power-Down Standby Current: one bank active; power-down mode;
IDD3P
CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and DM.
144
IDD3N
Active Standby Current: one bank active; active / precharge;CS >= VIH MIN;
CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and DQS inputs
changing twice per clock cycle; address and control inputs changing once per
clock cycle
Operating Current: one bank active; Burst = 2; reads; continuous burst; address
and control inputs changing once per clock cycle; 50% of data outputs changing
IDD4R _{on every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK}
= tCK MIN; IOUT = 0mA
Operating Current: one bank active; Burst = 2; writes; continuous burst; address
and control inputs changing once per clock cycle; 50% of data outputs changing
IDD4W _{on every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK}
= tCK MIN
IDD5
Auto-Refresh Current: tRC = tRFC MIN, distributed refresh
IDD6
Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK MIN
IDD7
Operating Current: four bank; four bank interleaving with BL=4;
Refer to the following page for detailed test conditions.
405
855
945
1530
22,5
1890
512MB
x72
1bank
-8
MAX
1620
1800
126
630
396
288
810
1710
1890
3060
45
3780
1GB
x72
2bank
-8
MAX
2430
2610
252
1260
792
576
1620
2520
2700
3870
90
4590
Unit ^Notes
5
mA 1, 4
mA 1, 3, 4
mA 2, 4
mA 2, 4
mA 2, 4
mA 2, 4
mA 2, 4
mA 1, 3, 4
mA 1, 4
mA 1, 4
mA 2, 4
mA 1, 3, 4
1. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component] for single bank modules (n: number of components per module bank)
n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank)
2. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component] for single bank modules (n: number of components per module bank)
2 * n * IDDx[component] for two bank modules (n: number of components per module bank)
3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
4. DRAM component currents only: module IDD will be measured differently depending upon register and PLL operation currents
5. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C
INFINEON Technologies
9
2002-08-16 (0.91)