HYS72D32500GR-7F-B Datasheet, PDF (12/22 Pages) Infineon Technologies AG – Low Profile Registered DDR-I SDRAM-Modules

HYS 72Dxx5xxGR-7F/7/8-B
Registered DDR-I SDRAM-Modules
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5V ± 0.2V; V_DD = 2.5V ± 0.2V)
Symbol
Parameter
DDR266F
-7F
Min Max
DDR266A
-7
Min Max
DDR200
-8
Min Max
t_AC
t_DQSCK
t_CH
t_CL
t_HP
t_CK
t_CK
t_DH
t_DS
t_IPW
t_DIPW
t_HZ
t_LZ
t_DQSS
t_DQSQ
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
Clock cycle time
CL = 2.5
CL = 2.0
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width (each input)
DQ and DM input pulse width (each input)
Data-out high-impedence time from CK/CK
Data-out low-impedence time from CK/CK
Write command to 1st DQS latching transition
DQS-DQ skew
(for DQS & associated DQ signals)
− 0.75 + 0.75
− 0.75 + 0.75
0.45 0.55
0.45 0.55
min (t_CL, t_CH)
7
12
7.5
12
0.5
0.5
2.2
1.75
− 0.75 + 0.75
− 0.75 + 0.75
0.75 1.25
− 0.75 + 0.75
− 0.75 + 0.75
0.45 0.55
0.45 0.55
min (t_CL, t_CH)
7
12
7.5
12
0.5
0.5
2.2
1.75
− 0.75 + 0.75
− 0.75 + 0.75
0.75 1.25
+ 0.5
+ 0.5
− 0.8 + 0.8
− 0.8 + 0.8
0.45 0.55
0.45 0.55
min (t_CL, t_CH)
8
12
10
12
0.6
0.6
2.5
2
− 0.8 + 0.8
− 0.8 + 0.8
0.75 1.25
+ 0.6
t_QHS
t_QH
t_DQSL,H
t_DSS
t_DSH
t_MRD
t_WPRES
t_WPST
t_WPRE
t_IS
Data hold skew factor
Data Output hold time from DQS
DQS input low (high) pulse width (write cycle)
t_HP-t_QHS
0.35
DQS falling edge to CK setup time (write cycle)
0.2
DQS falling edge hold time from CK (write cycle)
0.2
Mode register set command cycle time
14
Write preamble setup time
0
Write postamble
0.40
Write preamble
0.25
Address and control input setup
time
fast slew rate 0.9
slow slew rate 1.0
+ 0.75
0.60
t_HP-t_QHS
0.35
0.2
0.2
14
0
0.40
0.25
0.9
1.0
+ 0.75
0.60
t_HP-t_QHS
0.35
0.2
0.2
16
0
0.40
0.25
1.1
1.1
+ 1.0
0.60
fast slew rate 0.9
0.9
1.1
t_IH Address and control input hold time
slow slew rate 1.0
1.0
1.1
t_RPRE
t_RPST
t_RAS
t_RC
t_RFC
Read preamble
Read postamble
Active to Precharge command
Active to Active/Auto-refresh command period
Auto-refresh to Active/Auto-refresh
command period
0.9
0.40
45
60
1.1
0.60
120,000
0.9
0.40
45
65
1.1
0.60
120,000
0.9
0.40
50
70
1.1
0.60
120,000
75
75
80
t_RCD Active to Read or Write delay
15
20
20
t_RP Precharge command period
15
20
20
t_RRD Active bank A to Active bank B command
15
15
15
Unit Notes
ns 1-4
ns 1-4
t_CK
1-4
t_CK
1-4
ns 1-4
ns 1-4
ns 1-4
ns 1-4
ns 1-4
ns 1, 10
ns 1-4,11
ns 1-4, 5
ns 1-4, 5
t_CK
1-4
ns 1-4
ns 1-4
ns 1-4
t_CK
1-4
t_CK
1-4
t_CK
1-4
ns 1-4
ns 1-4, 7
t_CK 1-4, 6
t_CK
1-4
ns
ns _2-4,
ns ^10,11
ns
t_CK
1-4
t_CK
1-4
ns 1-4
ns 1-4
ns 1-4
ns 1-4
ns 1-4
ns 1-4
INFINEON Technologies
12
2002-08-16 (0.91)