HYS72D32500GR-7F-B Datasheet, PDF (10/22 Pages) Infineon Technologies AG – Low Profile Registered DDR-I SDRAM-Modules

HYS 72Dxx5xxGR-7F/7/8-B
Registered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (-7: PC2100)
Symbol
Parameter/Condition
256MB
x72
1bank
-7
MAX
Operating Current: one bank; active / precharge; tRC = tRC MIN; tCK = tCK MIN;
IDD0 DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs 900
changing once every two clock cycles
512MB
x72
1bank
-7
MAX
1800
1GB
x72
2bank
-7
MAX
2790
Unit ^Notes
5
mA 1, 4
IDD1
Operating Current: one bank; active/read/precharge; Burst = 4;
Refer to the following page for detailed test conditions.
990
1980
2970
mA 1, 3, 4
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE
IDD2P
<= VIL MAX; tCK = tCK MIN
72
144
288
mA 2, 4
Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle; CKE >= VIH
IDD2F MIN; tCK = tCK MIN ,address and other control inputs changing once per clock
360
cycle, VIN = VREF for DQ, DQS and DM.
Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle;
IDD2Q CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs stable at >= VIH 225
MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM.
720
1440
mA 2, 4
450
900
mA 2, 4
IDD3P
Active Power-Down Standby Current: one bank active; power-down mode; CKE
<= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and DM.
162
324
648
mA 2, 4
Active Standby Current: one bank active; active / precharge;CS >= VIH MIN; CKE
IDD3N >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and DQS inputs changing 495
twice per clock cycle; address and control inputs changing once per clock cycle
990
1980
mA 2, 4
IDD4R
Operating Current: one bank active; Burst = 2; reads; continuous burst; address
and control inputs changing once per clock cycle; 50% of data outputs changing on
every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK
MIN; IOUT = 0mA
Operating Current: one bank active; Burst = 2; writes; continuous burst; address
IDD4W ^{and control inputs changing once per clock cycle; 50% of data outputs changing on}
every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK
MIN
IDD5
IDD6
Auto-Refresh Current: tRC = tRFC MIN, distributed refresh
Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK MIN
IDD7
Operating Current: four bank; four bank interleaving with BL=4;
Refer to the following page for detailed test conditions.
1035
1125
1620
23
2025
2070
2250
3240
45
4050
3060
3240
4230
90
5040
mA 1, 3, 4
mA 1, 4
mA 1, 4
mA 2, 4
mA 1, 3, 4
1. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component] for single bank modules (n: number of components per module bank)
n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank)
2. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component] for single bank modules (n: number of components per module bank)
2 * n * IDDx[component] for two bank modules (n: number of components per module bank)
3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
4. DRAM component currents only: module IDD will be measured differently depending upon register and PLL operation currents
5. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C
INFINEON Technologies
10
2002-08-16 (0.91)