HYS64V64220GBDL Datasheet, PDF (9/13 Pages) Infineon Technologies AG – 144 pin SO-DIMM SDRAM Modules

HYS64V64220GBDL-7/7.5/8-D
144 pin SO-DIMM SDRAM Modules
Notes
1. For proper power-up see the operation section of the component sheet.
2. AC timing tests for LV-TTL versions have V_IL = 0.4 V and V_IH = 2.4 V with the timing referenced to
the 1.4 V crossover point. The transition time is measured between V_IH and V_IL. All AC
measurements assume t_T = 1 ns with the AC output load circuit shown in figure below. Specified
t_AC and t_OH parameters are measured with a 50 pF only, without any resistive termination and
with an input signal of 1V / ns edge rate between 0.8 V and 2.0 V.
C LOC K 1.4 V
tIH
tIS
t CH
2.4 V
0.4 V
tCL
t_T
INPUT
OUTPUT
1.4 V
tAC
tLZ
tA C
t OH
tHZ
1.4 V
IO.vsd
I/O
50 pF
Measurement conditions for
t_AC and t_OH
3. If clock rising time is longer than 1 ns, a time (t_T/2 − 0.5) ns has to be added to this parameter.
4. If t_T is longer than 1 ns, a time (t_T − 1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycles and depend on the operating frequency
of the clock, as follows: the number of clock cycles = specified value of timing period (counted in
fractions as a whole number)
6. Access time from clock t_AC is 4.6 ns for PC133 components with no termination and 0 pF load,
Data out hold time t_OH is 1.8 ns for PC133 components with no termination and 0 pF load.
7. It is recommended to use two clock cycles between the last data-in and the precharge command
in case of a write command without Auto-Precharge. One clock cycle between the last data-in
and the precharge command is also supported, but restricted to cycle times tck greater or equal
the specified twr value, where tck is equal to the actual system clock time
8. When a Write command with AutoPrecharge has been issued, a time of tdal(min) has be fullfilled
before the next Activate Command can be applied. For each of the terms, if not already an
integer, round up to the next highest integer. tck is equal to the actual system clock time.
9. All AC characteristics shown are for SDRAM components. An initial pause of 100µs is required
after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh
(CBR) cycles before the Mode Register Set Operation can begin.
10.AC timing tests have V_il = 0.4 V and V_ih = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between V_ih and V_il. All AC measurements assume t_T=1ns
Infineon Technologies
9
2002-08-06