HYS64V64220GBDL Datasheet, PDF (8/13 Pages) Infineon Technologies AG – 144 pin SO-DIMM SDRAM Modules

HYS64V64220GBDL-7/7.5/8-D
144 pin SO-DIMM SDRAM Modules
AC Characteristics 9)10)
T_A = 0 to 70 ^oC; V_SS = 0 V; V_DD, V_DDQ = 3.3 V ± 0.3 V, tT = 1 ns
T_A = 0 to 70 °C; V_SS = 0 V; V_DD = 3.3 V ± 0.3 V, t_T = 1 ns
Parameter
Symbol
Limit Values
Unit
Row Active Time
Row Cycle Time
Row Cycle Time during Auto
Refresh
Activate(a) to Activate(b)
Command period
CAS(a) to CAS(b) Command
period
-7
PC133-
222
-7.5
PC133-
333
-8
PC100-
222
min. max. min. max. min. max.
t_RAS 37 100k 45 100k 48 100k ns 5
t_RC 60 – 67 – 70 – ns 5
t_RFC 63
67
70
ns
t_RRD 14 – 15 – 16 – ns 5
t_CCD
1
–
1
–
1
– CLK
Refresh Cycle
Refresh Period (8192 cycles) t_REF – 64 – 64 – 64 ms
Self Refresh Exit Time
t_SREX
1
–
1
–
1
CLK
Read Cycle
Data Out Hold Time
t_OH
3
–
3
–
3
– ns 2,
6
Data Out to Low Impedance Time
t_LZ
0
–
0
–
0
– ns
Data Out to High Impedance Time
t_HZ
3
7
3
7
3
8 ns
DQM Data Out Disable Latency
t_DQZ
–
2
–
2
–
2 CLK
Write Cycle
Last Data Input to Precharge
(Write without AutoPrecharge)
t_WR 14 – 15 – 15 – ns 7
Last Data Input to Activate
(Write with AutoPrecharge)
t_DAL,min
CLK 8
DQM Write Mask Latency
t_DQW
0
–
0
–
0
– CLK
Infineon Technologies
8
2002-08-06