HYS64V64220GBDL Datasheet, PDF (6/13 Pages) Infineon Technologies AG – 144 pin SO-DIMM SDRAM Modules

HYS64V64220GBDL-7/7.5/8-D
144 pin SO-DIMM SDRAM Modules
Operating Currents per memory bank
(T_A = 0 to 70^oC, V_DD = 3.3V ± 0.3V)
(Recommended Operating Conditions unless otherwise noted)
Parameter & Test Condition
Symb.
OPERATING CURRENT
trc=trcmin.,
All banks operated in random access,
all banks operated in ping-pong manner
PRECHARGE STANDBY CURRENT tck = min.
in Power Down Mode
ICC1
ICC2P
CS =VIH (min.), CKE<=Vil(max)
PRECHARGE STANDBY CURRENT
in Non-Power Down Mode
tck = min.
ICC2N
CS = VIH (min.), CKE>=Vih(min)
NO OPERATING CURRENT
CKE>=VIH(min.) ICC3N
tck = min., CS = VIH(min),
active state ( max. 4 banks)
CKE<=VIL(max.) ICC3P
64Mx64
512Mbyte
PC133 PC100
Note
1840
16
1360 mA ^{1, 2}
1
16 mA
240 mA 1
320
400
360 mA 1
80
80 mA 1
BURST OPERATING CURRENT
tck = min.,
Read command cycling
ICC4 1200
800 mA ^{1, 2}
AUTO REFRESH CURRENT
tck = min., trc = trcmin.
Auto Refresh command cycling
ICC5
1920
mA 1
1760
SELF REFRESH CURRENT
Self Refresh Mode, CKE=0.2V
tck =infinity
ICC6
14
14 mA 1
Notes:
1. These parameters depend on the cycle rate. These values are measured at 133 MHz operation frequency for PC133
and at 100MHz for PC100 modules. Input signals are changed once during tck, excepts for ICC6 and for standby currents
when tck=infinity.
2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4
is assumed and the data-out current is excluded.
Infineon Technologies
6
2002-08-06