TLF4949 Datasheet, PDF (8/23 Pages) Infineon Technologies AG – 5V Low Drop Out Linear Voltage Regulator

TLF4949
General Product Characteristics
4.2
Functional Range
Table 1
Pos. Parameter
Symbol
Limit Values
Unit Conditions
Min.
Max.
4.2.1 Input Voltage Range for Normal V_IN
5.5
Operation
28
V
–
4.2.2 Extended Input Voltage Range
V_IN
3.5
40
V
–^{1) 2)}
1) The output voltage will follow the input voltage for input voltages below V_OUT + V_DR, i.e device is in tracking mode until
V_OUT + V_DR is reached.
2) Input voltages ranging from > 28 V up to 40 V may only be applied for transient periods t_TR < 1s.
Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the Electrical Characteristics table.
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Pos. Parameter
Symbol
Limit Values
Unit Conditions
Min. Typ. Max.
TLF4949SJ (PG-DSO-8)
4.3.3
4.3.4
4.3.5
Junction to Soldering Point¹⁾
Junction to Ambient¹⁾
R_thJSP
–
R_thJA
–
–
71
–
116 –
172 –
K/W
K/W
K/W
–
–²⁾
Footprint only³⁾
4.3.6
–
145 –
K/W 300 mm² heatsink
area on PCB³⁾
4.3.7
–
139 –
K/W 600 mm² heatsink
area on PCB³⁾
TLF4949EJ (PG-DSO-8 Exposed Pad)
4.3.1
4.3.2
4.3.3
Junction to Case¹⁾
Junction to Ambient¹⁾
R_thJC
–
R_thJA
–
–
19
–
52
–
167 –
K/W
K/W
K/W
–
–⁴⁾
Footprint only³⁾
4.3.4
–
78
–
K/W 300 mm² heatsink
area on PCB³⁾
4.3.5
–
66
–
K/W 600 mm² heatsink
area on PCB³⁾
Thermal Shutdown
4.3.6 Junction Temperature
T_JSD
–
165 –
°C
1)
1) Not subject to production test, specified by design.
2) Specified R_thJA value is according to Jedec JESD51-2,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
3) Specified R_thJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm³ board with 1 copper layer (1 x 70µm Cu).
4) Specified R_thJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
Data Sheet
8
Rev. 1.0, 2012-05-07