TLF4949 Datasheet, PDF (17/23 Pages) Infineon Technologies AG – 5V Low Drop Out Linear Voltage Regulator

TLF4949
Application Information
6,00
T_J = 25 V
5,00
4,00
3,00
2,00
1,00
0,00
0
0,05
0,1
0,15
0,2
0,25
0,3
I_OUT [A]
Figure 7 Foldback Characteristics of V_OUT
Preregulator
To improve the transient immunity a preregulator stabilizes the internal supply voltage to 5V. This internal voltage
is also present at the PRE pin (Pin 3). This voltage should not be used as an output because the output capability
is very small (≤ 10 µA).
This output at the PRE pin may be used as an option when an improved transient behavior for supply voltages
less than 8V is desired. In this case a capacitor (100nF -1µF) can be connected between the PRE pin and GND.
At the same time the usage of such a bypass capacitor is suitable to reduce output noise at the OUT pin. If this
feature is not used the PRE pin must be left open.
Reset Circuit
The block circuit diagram of the reset circuit is shown in Figure 8 “Reset Circuit” on Page 18. The reset circuit
supervises the output voltage. The reset threshold of 4.5V is defined by the internal reference voltage and standby
output divider. The reset pulse delay time t_RD, is defined by the charge time of an external capacitor C_D:
t_RD
=
C-----_D----×_{-----2---.--0----V---}
2.0 µA
The reaction time of the reset circuit originates from the discharge time limitation of the reset capacitor C_D and is
proportional to the value of C_D.
Data Sheet
17
Rev. 1.0, 2012-05-07