TLF4949 Datasheet, PDF (5/23 Pages) Infineon Technologies AG – 5V Low Drop Out Linear Voltage Regulator

3
Pin Configuration
3.1
Pin Assignment PG-DSO-8
IN
1
SI
2
PRE
3
D
4
Figure 2 Pin Configuration PG-DSO-8
8
OUT
7
SO
6
RO
5
GND
PG-DSO-8.vsd
TLF4949
Pin Configuration
3.2
Pin Definitions and Functions PG-DSO-8
Pin
Symbol
Function
1
IN
Input; block to GND directly at the IC with a ceramic capacitor.
2
SI
Sense Input; if not needed connect to OUT
3
PRE
Preregulator Output;
4
D
Reset Delay; to select delay time, connect to GND via capacitor.
5
GND
Ground
6
RO
Reset Output; open-collector output. Keep open, if not needed.
7
SO
8
OUT
Sense Output; open-collector output. Keep open, if not needed.
5-V Output; connect to GND with a capacitor ≥ 4.7μF, ESR < 10 Ω.^{1) 2)}
1) For the usage of capacitors with very low ESR-values it is recommended to use a small 1Ω resistor in series.
2) Measured at f = 10kHz.
Data Sheet
5
Rev. 1.0, 2012-05-07