TLE6240GP Datasheet, PDF (8/23 Pages) Infineon Technologies AG – Smart 16-fold Low-Side Switch

Data Sheet TLE 6240 GP
rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever
chip select CS makes any transition.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI infor-
mation is read in on the falling edge of SCLK. Input data is latched in the shift register and
then transferred to the control buffer of the output stages.
The input data consist of 16 bit, made up of one control byte and one data byte. The control
byte is used to program the device, to operate it in a certain mode as well as providing diag-
nostic information (see page 14). The eight data bits contain the input information for the eight
channels, and are high active.
SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant
bit first. SO is in a high impedance state until the CS pin goes to a logic low state. New diag-
nostic data will appear at the SO pin following the rising edge of SCLK.
RESET - Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and
switches all outputs OFF. An internal pull-up structure is provided on chip.
Output Stage Control
The 16 outputs of the TLE 6240 GP can be controlled via serial interface. Additionally eight of
these 16 channels can alternatively be controlled in parallel (Channel 1to 4 and 9 to 12) for
PWM applications.
Parallel Control
A Boolean operation (either AND or OR) is performed on each of the parallel inputs and re-
spective SPI data bits, in order to determine the states of the respective outputs. The type of
Boolean operation performed is programmed via the serial interface.
The parallel inputs are high or low active depending on the PRG pin. If the parallel input pins
are not connected (independent of high or low activity) it is guaranteed that the outputs 1 to 4
and 9 to 12 are switched off. The PRG pin itself is internally pulled up when it is not con-
nected.
PRG - Program pin.
PRG = High (V_S): Parallel inputs Channel 1to 4 and 9 to 12 are
high active
PRG = Low (GND): Parallel inputs Channel 1 to 4 and 9 to 12 are
low active.
V3.1
Page 8
26.Aug 2002