TLE6240GP Datasheet, PDF (7/23 Pages) Infineon Technologies AG – Smart 16-fold Low-Side Switch

Data Sheet TLE 6240 GP
Functional Description
The TLE 6240 GP is an 16-fold low-side power switch which provides a serial peripheral in-
terface (SPI) to control the 16 power DMOS switches, and diagnostic feedback. The power
transistors are protected against short to V_BB, overload, overtemperature and against over-
voltage by active zener clamp.
The diagnostic logic recognizes a fault condition which can be read out via the serial diagnos-
tic output (SO).
Circuit Description
Power Transistor Protection Functions⁷⁾
Each of the 16 output stages has its own zener clamp, which causes a voltage limitation at the
power transistor when solenoid loads are switched off. The outputs are provided with a current
limitation set to a minimum of 1 A for channels 1 to 8 and 3 A for channels 9 to16.
Each output is protected by embedded protection functions. In the event of an overload or
short to supply, the current is internally limited and the corresponding bit combination is set
(early warning). If this operation leads to an overtemperature condition, a second protection
level (about 170 °C) will change the output into a low duty cycle PWM (selective thermal shut-
down with restart) to prevent critical chip temperatures.
SPI Signal Description
CS - Chip Select. The system microcontroller selects the TLE 6240 GP by means of the CS
pin. Whenever the pin is in a logic low state, data can be transferred from the µC and vice
versa.
CS High to Low transition: - Diagnostic status information is transferred from the power
outputs into the shift register.
- Serial input data can be clocked in from then on.
- SO changes from high impedance state to logic high or low
state corresponding to the SO bits.
CS Low to High transition: - Transfer of SI bits from shift register into output buffers
.
To avoid any false clocking the serial clock input pin SCLK should be logic low state during
high to low transition of CS . When CS is in a logic high state, any signals at the SCLK and SI
pins are ignored and SO is forced into a high impedance state.
SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE
6240 GP. The serial input (SI) accepts data into the input shift register on the falling edge of
SCLK while the serial output (SO) shifts diagnostic information out of the shift register on the
7 ) _{The integrated protection functions prevent an IC destruction under fault conditions and may not be used in normal operation or perma-}
nently
V3.1
Page 7
26.Aug 2002