PEB20560 Datasheet, PDF (76/433 Pages) Infineon Technologies AG – ICs for Communications

PEB 20560
Functional Block Description
Receive Status Byte in Clock Mode 3
In clock mode 3 the receive status byte is modified when it is copied into RFIFO. It
contains the following information:
bit 7
VFR
RDO
CRC
bit 0
CHAD4 CHAD3 CHAD2 CHAD1 CHAD0
VFR
Valid Frame.
Indicates whether the received frame is valid (‘1’) or not (‘0’ invalid).
A frame is invalid when
– its length is not an integer multiple of 8 bits (n × 8 bits), e.g. 25 bit,
– it is too short, depending on the selected operation mode (transparent
mode 0: 2 bytes minimum),
the frame was aborted from the transmitting station.
RDO
Receive Data Overflow.
A ‘1’ indicates, that a RFIFO-overflow has occurred within the actual frame.
CRC
CRC Compare Check.
0: CRC check failed, received frame contains errors.
1: CRC check o.k., received frame is error free.
CHAD4…0 Channel Address 4…0.
CHAD4…0 identifies on with IOM-port/channel the corresponding frame
was received:
CHAD4…3: IOM-port number (3 - 0) of ELIC (≠ DOC port number)
CHAD2…0: IOM-channel number (7 - 0)
Note: The contents of the receive status register is not changed.
2.1.2.4.7 Serial Port Configuration
The SACCO supports different serial port configuration, enabling the use of the circuit in
– point-to-point configurations
– point-to-multi-point configurations
– multi master configurations
Point-to-Point Configuration
The SACCO transmits frames without collision detection/resolution.
(CCR1:SC1, SC0: 00)
Additionally the input CxD can be used as a “clear to send” strobe. Transmission is
inhibited by a ‘1’ on the CxD-input. If “CxD” becomes ‘1’ during the transmission of a
frame, the frame is aborted and IDLE is transmitted. The CxD-pin is evaluated with the
Semiconductor Group
2-30
2003-08