PEB20560 Datasheet, PDF (212/433 Pages) Infineon Technologies AG – ICs for Communications

PEB 20560
Operational Description
data rates. A CFI reference clock (CRCL) is generated out of the PDC-clock. The
PCM-framing signal PFS is used to synchronize the CFI-frame structure. Additionally,
the EPIC-1 generates clock and framing signals as outputs to operate the connected
subscriber circuits such as layer-1 and codec filter devices. The generated data clock
DCL has a frequency equal to or twice the CFI-data rate.
Note that if PFS is selected as the framing signal source, the FSC-signal is an output
with a fixed timing relationship with respect to the CFI-data lines. The relationship
between FSC and the CFI-frame depends only on the selected FSC-output wave form
(CMD2- register). The CFI-offset function shifts both the frame and the FSC-output
signal with respect to the PFS-signal.
In the second case, the CFI-data rate is derived from the DCL-clock, which is now used
as an input signal. The DCL-clock may also first be divided down by internal prescalers
before it serves as the CFI reference clock CRCL and before defining the CFI-data rate.
The framing signal FSC is used to synchronize the CFI-frame structure.
3.1.3.3 Switching Functions
The major tasks of the EPIC-1 part is to dynamically switch PCM-data between the serial
PCM-interface, the serial configurable interface (CFI) and the parallel µP-interface. All
possible switching paths are shown in Figure 3-2.
EPIC ^R
1
2
C
P
F
3
4
C
I
5
M
6
µP Interface
µP
ITS05844
Figure 3-2 Switching Paths Inside the EPIC^®-1
Note that the time-slot selections in upstream direction are completely independent of
the time-slot selections in downstream direction.
Semiconductor Group
3-6
2003-08