PEB20560 Datasheet, PDF (296/433 Pages) Infineon Technologies AG – ICs for Communications

PEB 20560
Description of Registers
MFFI
MAC
PFI
PIM
SIN
SOV
MFFIFO-Interrupt; the last MF-channel command (issued by CMDR:MFT1,
MFT0) has been executed and the EPIC-1 is ready to accept the next
command. Additional information can be read from STAR:MFTO…MFFE.
MFFI is reset by reading ISTA.
Monitor Channel Active interrupt; the EPIC-1 has found an active monitor
channel. A new search can be started by reissuing the CMDR:MFSO-
command. MAC is reset by reading ISTA.
PCM-Framing Interrupt; the STAR:PSS-bit has changed its polarity. To
determine whether the PCM-interface is synchronized or not, STAR must be
read. The PFI-bit is reset by reading ISTA.
PCM-Input Mismatch; this interrupt is generated immediately after the
comparison logic has detected a mismatch between a pair of PCM-input
lines. The exact reason for the interrupt can be determined by reading the
PICM-register. Reading ISTA clears the PIM-bit. A new PIM-interrupt can
only be generated after the PICM-register has been read.
Synchronous transfer Interrupt; The SIN-interrupt is enabled if at least one
synchronous transfer channel (A and/or B) is enabled via the STCR:TAE,
TBE-bits. The SIN-interrupt is generated when the access window for the µP
opens. After the occurrence of the SIN-interrupt the µP can read and/or write
the synchronous transfer data registers (STDA, STDB). The SIN-bit is reset
by reading ISTA.
Synchronous transfer Overflow; The SOV-interrupt is generated if the µP
fails to access the data registers (STDA, STDB) within the access window.
The SOV-bit is reset by reading ISTA.
5.1.1.4.31 Mask Register EPIC^®-1 (MASK_E)
Access: write
Reset value: 00_H
bit 7
bit 0
TIN
SFI
MFFI MAC
PFI
PIM
SIN
SOV
A logical 1 disables the corresponding interrupt as described in the ISTA-register.
A masked interrupt is stored internally and reported in ISTA immediately if the mask is
released. However, an SFI-interrupt is also reported in ISTA if masked. In this case no
interrupt is generated. When writing register MASK_E while ISTA_E indicates a non
masked interrupt INT is temporarily set into the inactive state.
Semiconductor Group
5-53
2003-08