PEB20560 Datasheet, PDF (276/433 Pages) Infineon Technologies AG – ICs for Communications

PEB 20560
Description of Registers
5.1.1.4.8 Configurable Interface Mode Register 2 (CMD2)
Access: read/write
Reset value: 00_H
bit 7
FC2
FC1
FC0
COC
0
bit 0
0
CBN9 CBN8
FC2…0
Framing output Control.
Given that CMD1:CSS = 0, these bits determine the position of the
FSC-pulse relative to the CFI-frame, as well as the type of FSC-pulse
generated. The position and width of the FSC-signal with respect to the
CFI-frame can be found in the following two Figure 5-2 and Figure 5-3.
CFI
Frame
RCL
DCL
DCL
DCL
Last Time-Slot of a Frame
Time-Slot 0
Conditions:
CFI Mode 0; CMD2 : COC = 1
CFI Modes 1, 2; CMD2 : COC = 0
CFI Mode 0; CMD2 : COC = 0
CFI Mode 3; CMD2 : COC = 1
CFI Mode 3; COC = 0
FSC
CMD2 : FC2...0 = 011 (FC mode 3)
FSC
CMD2 : FC2...0 = 010 (FC mode 6)
ITD05851
Figure 5-2 Position of the FSC-Signal for FC-Modes 3 and 6
Time-Slot
CFI
0
1
2
3
4
5
Frame
FSC
Conditions:
CMD2 : FC2...0 = 110 (FC mode 6)
RCL
Figure 5-3 Position of the FSC-Signal for FC-Mode 6
ITD05852
Semiconductor Group
5-33
2003-08