XC167CI-16F_06 Datasheet, PDF (70/90 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core

4.4
AC Parameters
XC167CI-16F
Derivatives
Electrical Parameters
4.4.1 Definition of Internal Timing
The internal operation of the XC167 is controlled by the internal master clock f_MC.
The master clock signal f_MC can be generated from the oscillator clock signal f_OSC via
different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate f_MC.
This influence must be regarded when calculating the timings for the XC167.
Phase Locked Loop Operation (1:N)
f _OSC
f _MC
Direct Clock Drive (1:1)
f _OSC
TCM
f _MC
Prescaler Operation (N:1)
f _OSC
TCM
f _MC
TCM
MCT05555
Figure 15 Generation Mechanisms for the Master Clock
Note: The example for PLL operation shown in Figure 15 refers to a PLL factor of 1:4,
the example for prescaler operation refers to a divider factor of 2:1.
The used mechanism to generate the master clock is selected by register PLLCON.
CPU and EBC are clocked with the CPU clock signal f_CPU. The CPU clock can have the
same frequency as the master clock (f_CPU = f_MC) or can be the master clock divided by
two: f_CPU = f_MC / 2. This factor is selected by bit CPSYS in register SYSCON1.
Data Sheet
68
V1.3, 2006-08