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XC167CI-16F_06 Datasheet, PDF (25/90 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core | |||
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XC167CI-16F
Derivatives
Functional Description
RH7) so-called General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,
any location in the DPRAM is bitaddressable.
1024 bytes (2 Ã 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC166 Family. Therefore, they should
either not be accessed, or written with zeros, to ensure upward compatibility.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 12 Mbytes (approximately, see Table 3) of external RAM and/or ROM can
be connected to the microcontroller. The External Bus Interface also provides access to
external peripherals.
Table 3
XC167 Memory Map1)
Address Area
Start Loc.
Flash register space FFâF000H
Reserved (Access trap) F8â0000H
End Loc.
FFâFFFFH
FFâEFFFH
Area Size2)
4 Kbytes
Notes
3)
< 0.5 Mbytes Minus Flash
registers
Reserved for PSRAM
Program SRAM
Reserved for pr. mem.
Program Flash
Reserved
External memory area
E0â0800H
E0â0000H
C2â0000H
C0â0000H
BFâ0000H
40â0000H
F7âFFFFH
E0â07FFH
DFâFFFFH
C1âFFFFH
BFâFFFFH
BEâFFFFH
< 1.5 Mbytes Minus PSRAM
2 Kbytes
Maximum
< 2 Mbytes Minus Flash
128 Kbytes â
64 Kbytes â
< 8 Mbytes Minus reserved
segment
External IO area4)
20â0800H 3FâFFFFH < 2 Mbytes Minus TwinCAN
TwinCAN registers
20â0000H 20â07FFH 2 Kbytes
â
External memory area 01â0000H 1FâFFFFH < 2 Mbytes Minus segment 0
Data RAMs and SFRs 00â8000H 00âFFFFH 32 Kbytes Partly used
External memory area 00â0000H 00â7FFFH 32 Kbytes â
1) Accesses to the shaded areas generate external bus accesses.
2) The areas marked with â<â are slightly smaller than indicated, see column âNotesâ.
3) Not defined register locations return a trap code.
4) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
peripherals properly.
Data Sheet
23
V1.3, 2006-08
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