TDA5252G2 Datasheet, PDF (66/86 Pages) Infineon Technologies AG – ASK/FSK 915MHz Wireless Transceiver

TDA5252 G2
Version 1.1
Application
Note 1: Chip internal signal „Sequencer enables data detection“ has a LOW to HIGH transition
about 2.6ms after RX is activated (see Figure 2-15).
Note 2: The positive edge of the „Window Count Complete“ signal latches the result of comparison
of the analog to digital converted RSSI voltage with TH3 (register 08H). A logic combination of this
output and the result of the comparison with single/double THx defines the internal signal
„data_valid“.
Figure 3-27 shows that the logic is ready for the next conversion after 3 periods of the data signal.
Timing in Single Shot mode can be seen in the subsequent figure:
Data
Sequenzer enables
data detection
Counter Reset
reset
Gate time
Compare with single
TH and latch result
Compare with double
TH and latch result
(Frequency) Window
Count Complete
start of conversion
count
comp.
comp.
ready*
no possible start of next conversion
because of Single Shot Mode
Figure 3-29 Frequency Detection timing in Single Shot mode
t
t
t
t
t
t
t
Frequ_Detect_Timing_singleShot_wmf
3.7.1 Frequency Window for Data Rate Detection
The high time of data is used to measure the frequency of the data signal. For Manchester coding
either the data frequency or half of the data frequency have to be detected corresponding to one
high time or twice the high time of data signal.
A time period of 3*2*T is necessary to decide about valid or invalid data.
T
2*T
DATA
0
0
1
T2
T1
possible
GATE 1
0
2*T2
2*T1
possible
GATE 2
0
1
t
0
t
t
Data Sheet
66
2007-02-26