TDA5252G2 Datasheet, PDF (19/86 Pages) Infineon Technologies AG – ASK/FSK 915MHz Wireless Transceiver

TDA5252 G2
Version 1.1
Functional Description
2.4.5 PLL Synthesizer
The Phase Locked Loop synthesizer consists of two VCOs (i.e. transmit and receive VCO), a
divider by 4, an asynchronous divider chain with selectable overall division ratio, a phase detector
with charge pump and a loop filter and is fully implemented on-chip. The VCOs are including spiral
inductors and varactor diodes. The center frequency of the transmit VCO is 915MHz, the center
frequency of the receive VCO is 1220MHz.
Generally in receive mode the relationship between local oscillator frequency fosc, the receive RF
frequency fRF and the IF frequency fIF and thus the frequency that is applied to the I/Q Mixers is
given in the following formula:
f_osc = 4/3 f_RF = 4 f_IF
[2 – 1]
The VCO signal is applied to a divider by 4 which is producing approximately 305MHz signals in
quadrature. The overall division ratio of the divider chain following the divider by 4 is 12 in transmit
mode and 16 in receive mode as the nominal crystal oscillator frequency is 19.0625MHz. The
division ratio is controlled by the RxTx pin (pin 5) and the D10 bit in the CONFIG register.
2.4.6 I/Q Filters
The I/Q IF to zero-IF mixers are followed by baseband 6^th order low pass filters that are used for
RF-channel filtering.
OP
INTERNAL BUS
iq_filter.wmf
Figure 2-3 One I/Q Filter stage
The bandwidth of the filters is controlled by the values set in the filter-register. It can be adjusted
between 50 and 350kHz in 50kHz steps via the bits D1 to D3 of the LPF register (subaddress 03H).
2.4.7 I/Q Limiters
The I/Q Limiters are DC coupled multistage amplifiers with offset-compensating feedback circuit
and an overall gain of approximately 80dB each in the frequency range of 100Hz up to 350kHz.
Data Sheet
19
2007-02-26