TDA5252G2 Datasheet, PDF (21/86 Pages) Infineon Technologies AG – ASK/FSK 915MHz Wireless Transceiver

TDA5252 G2
Version 1.1
Functional Description
ASK / FSK
OTA
INTERNAL BUS
Figure 2-5 Data Filter architecture
data_filter.wmf
2.4.10 Data Slicer
The data slicer is a fast comparator with a bandwidth of 100kHz. The self-adjusting threshold is
generated by a RC-network (LPF) or by use of one or both peak detectors depending on the
baseband coding scheme. This can be controlled by the D15 bit of the CONFIG register as shown
in the following table.
Table 2-4
Bit
D15
Sub Address 00H: CONFIG
Function
Description
SLICER
0= Lowpass Filter, 1= Peak Detector
Default
0
2.4.11 Peak Detectors
Two separate Peak Detectors are available. They are generating DC voltages in a fast-attack and
slow-release manner that are proportional to the positive and negative peak voltages appearing in
the data signal. These voltages may be used to generate a threshold voltage for non-Manchester
encoded signals, for example. The time-constant of the fast-attack/slow-release action is
determined by the RC network with external capacitor.
2.4.12 Crystal Oscillator
The reference oscillator is an NIC oscillator type (Negative Impedance Converter) with a crystal
operating in serial resonance. The nominal operating frequency of 19.0625MHz and the
frequencies for FSK modulation can be adjusted via 3 external capacitors. Via microcontroller and
bus interface the chip-internal capacitors can be used for finetuning of the nominal and the FSK
modulation frequencies. This finetuning of the crystal oscillator allows to eliminate frequency errors
due to crystal or component tolerances.
2.4.13 Bandgap Reference Circuitry and Powerdown
A Bandgap Reference Circuit provides a temperature stable 1.2V reference voltage for the device.
A power down mode is available to switch off all subcircuits that are controlled by the bidirectional
Powerdown&DataDetect PwdDD pin (pin 27) as shown in the following table. Power down mode
can either be activated by pin 27 or bit D14 in Register 00h. In power down mode also pin 28 (DATA)
is affected (see Section 2.4.17).
Data Sheet
21
2007-02-26