TDA5252G2 Datasheet, PDF (59/86 Pages) Infineon Technologies AG – ASK/FSK 915MHz Wireless Transceiver

TDA5252 G2
Version 1.1
Application
3.5
Limiter and RSSI
The I/Q Limiters are DC coupled multistage amplifiers with offset-compensating feedback circuit
and an overall gain of approximately 80dB each in the frequency range of 100Hz up to 350kHz.
Receive Signal Strength Indicator (RSSI) generators are included in both limiters which produce DC
voltages that are directly proportional to the input signal level in the respective channels. The
resulting I- and Q-channel RSSI-signals are summed to the nominal RSSI signal.
C_c
C_c
38 37 36
C_c
35 34
C_c
33 32
C
RSSI
31
29 RSSI
I- Filter
fg
Q- Filter
fg
I
Limiter
Q
Limiter
Quadr.
Corr.
Quadr.
Corr.
37k
SUM
limiter input.wmf
Figure 3-19 Limiter and Pinning
The DC offset compensation needs 2.2ms after Power On or Tx/Rx switch. This time is hard wired
and independent from external capacitors CC on pins 31 to 38. The maximum value for this
capacitors is 47nF.
RSSI accuracy settling time = 2.2ms + 5*RC=2.2ms+5*37k*2.2nF=2.6ms
R - internal resistor; C - external capacitor at Pin 29
Table 3-11
Cc
[nF]
220
100
47
22
10
Limiter Bandwidth
f3dB
lower limit
[Hz]
100
220
470
1000
2200
f3dB
upper
limit
IQ Filter
- ll -
- ll -
- ll -
- ll -
Comment
setup time not guaranteed
setup time not guaranteed
Eval Board
Data Sheet
59
2007-02-26