TDA5251F1 Datasheet, PDF (66/88 Pages) Infineon Technologies AG – ASK/FSK 315MHz Wireless Transceiver

TDA5251 F1
Version 1.0
Confidential
Application
Timing for data detection looks like the following. Two settings are possible: „Continuous“ and
„Single Shot“, which can be set by D5 and D6 in register 00H.
Data
Sequenzer enables
data detection
Counter Reset
reset
Gate time
Compare with single
TH and latch result
Compare with double
TH and latch result
(Frequency) Window
Count Complete
start of conversion
reset
count
comp.
com p.
ready*
possible start of next conversion
t
t
t
count
t
com p.
t
t
t
Frequ_Detect_Timing_continuous.wmf
Figure 3-29 Frequency Detection timing in continuous mode
Note 1: Chip internal signal „Sequencer enables data detection“ has a LOW to HIGH transition
about 2.6ms after RX is activated (see Figure 2-15).
Note 2: The positive edge of the „Window Count Complete“ signal latches the result of comparison
of the analog to digital converted RSSI voltage with TH3 (register 08H). A logic combination of this
output and the result of the comparison with single/double THx defines the internal signal
„data_valid“.
Figure 3-29 shows that the logic is ready for the next conversion after 3 periods of the data signal.
Timing in Single Shot mode can be seen in the subsequent figure:
Data
Sequenzer enables
data detection
Counter Reset
reset
Gate time
Compare with single
TH and latch result
Compare with double
TH and latch result
(Frequency) Window
Count Complete
start of conversion
count
comp.
comp.
re a d y *
no po ssible sta rt of n ext conve rsio n
because of S ingle Shot M ode
Figure 3-30 Frequency Detection timing in Single Shot mode
t
t
t
t
t
t
t
Frequ_Detect_Timing_singleShot_wmf
Preliminary Specification
66
2003-02-18