TDA5251F1 Datasheet, PDF (21/88 Pages) Infineon Technologies AG – ASK/FSK 315MHz Wireless Transceiver

TDA5251 F1
Version 1.0
Confidential
Functional Description
2.4.9 Data Filter
The 2-pole data filter has a Sallen-Key architecture and is implemented fully on-chip. The bandwidth
can be adjusted between approximately 5kHz and 102kHz via the bits D4 to D7 of the LPF register
as shown in Table 3-10.
ASK / FSK
OTA
INTERNAL BUS
Figure 2-5 Data Filter architecture
data_filter.wmf
2.4.10 Data Slicer
The data slicer is a fast comparator with a bandwidth of 100kHz. The self-adjusting threshold is
generated by a RC-network (LPF) or by use of one or both peak detectors depending on the
baseband coding scheme as described in Section 3.6. This can be controlled by the D15 bit of the
CONFIG register as shown in the following table.
Table 2-4
Bit
D15
Sub Address 00H: CONFIG
Function
Description
SLICER
0= Lowpass Filter, 1= Peak Detector
Default
0
2.4.11 Peak Detectors
Two separate Peak Detectors are available. They are generating DC voltages in a fast-attack and
slow-release manner that are proportional to the positive and negative peak voltages appearing in
the data signal. These voltages may be used to generate a threshold voltage for non-Manchester
encoded signals, for example. The time-constant of the fast-attack/slow-release action is
determined by the RC network with external capacitor.
2.4.12 Crystal Oscillator
The reference oscillator is an NIC oscillator type (Negative Impedance Converter) with a crystal
operating in serial resonance. The nominal operating frequency of 13.125MHz and the frequencies
for FSK modulation can be adjusted via 3 external capacitors. Via microcontroller and bus interface
the chip-internal capacitors can be used for finetuning of the nominal and the FSK modulation
frequencies. This finetuning of the crystal oscillator allows to eliminate frequency errors due to
crystal or component tolerances.
Preliminary Specification
21
2003-02-18