TDA5251F1 Datasheet, PDF (64/88 Pages) Infineon Technologies AG – ASK/FSK 315MHz Wireless Transceiver

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Component calculation: (rule of thumb)
TDA5251 F1
Version 1.0
Application
CP
³
2 * TL₁
100 k W
T_L1 – longest period of no signal change (LOW signal)
[3 – 34]
Cn
³
2 *TL₂
100 kW
T_L2 – longest period of no signal change (HIGH signal)
[3 – 35]
3.6.3 Peak Detector - Analog output signal
The TDA5251 data output can be digital (pin 28) or in analog form by using the peak detector output
and changing some settings.
To get an analog data output the slicer must be set to lowpass mode (Reg. 0, D15 = LP = 0) and
the peak detector capacitor at pin 12 or 13 has to be changed to a resistor of about 47kOhm.
DataSlicer
+
-
Slicer Threshold
Contr.
Logic
DATA
28
+ Peak
Detector
Data
Filter
Signal 100k
R
- Peak
Detector
PDP
13
100k
100k
SLC
14
PDN
12
Vcc
47k
C_SLC
Figure 3-26 Peak Detector as analog Buffer (v=1)
PkD_analog.wmf
3.6.4 Peak Detector – Power Down Mode
For a safe and fast threshold value generation the peak detector is turned on by the sequencer
circuit (see Section 2.4.18) only after the entire receiving path is active.
In the off state the output of the positive peak detector is tied down to GND and the output of the
negative peak detector is pulled up to VCC.
Preliminary Specification
64
2003-02-18