TDA5251F1 Datasheet, PDF (32/88 Pages) Infineon Technologies AG – ASK/FSK 315MHz Wireless Transceiver

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TDA5251 F1
Version 1.0
Functional Description
0,5*TH1 T_GATE 0,5*TH2
TH1 T_GATE TH2
RSSI TH3
DATA VALID
data_valid.wmf
Figure 2-13 Data Valid Circuit
D_OUT and RX_DATA_INV from the CONFIG register determine the output of data at Pin 28.
RxTxint and TX_ON are internally generated signals.
In RX and power down mode Data pin (Pin 28) is tied to GND.
RxTxint
RX_DATA_INV
RX DATA
DATA VALID
D_OUT
TX DATA
Data
28
TX ON
Figure 2-14 Data Input/Output Circuit
data_switch.wmf
2.4.18 Sequence Timer
The sequence timer has to control all the enable signals of the analog components inside the chip.
The time base is the 32 kHz RC oscillator.
After the first POWER ON or RESET a 730kHz clock is available at the clock output pin. This clock
output can be used by an external mP to set the system into the desired state and outputs valid data
after 500 µs (see Figure 2-15 and Figure 2-16, tCLKSU)
There are two possibilities to start the device after a reset or first power on:
- PWDDD pin is LOW: Normal operation timing is performed after t_SYSSU (see Figure 2-15).
- PWDDD pin is HIGH (device in power down mode): A clock is offered at the clock output pin
until the device is activated (PWDDD pin is pulled to LOW). After the first activation the time
t_SYSSU is required until normal operation timing is performed (see Figure 2-16 ).
This could be used to extend the clock generation without device programming or activation.
Note: It is required to activate the device for the duration of t_SYSSU after first power on or a reset.
Only if this is done the normal operation timing is performed.
Preliminary Specification
32
2003-02-18