XC2385A_14 Datasheet, PDF (53/141 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

XC2385A, XC2387A
XC2000 Family / Base Line
Functional Description
8 Kbytes of on-chip Stand-By SRAM (SBRAM) provide storage for system-relevant
user data that must be preserved while the major part of the device is powered down.
The SBRAM is accessed via a specific interface and is powered in domain M.
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are word-wide registers which are
used to control and monitor functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC2000 Family. In order to ensure
upward compatibility they should either not be accessed or written with zeros.
The on-chip Flash memory stores code, constant data, and control data. The on-chip
Flash memory consists of 1 module of 64 Kbytes (preferably for data storage) and
modules with a maximum capacity of 256 Kbytes each. Each module is organized in
sectors of 4 Kbytes.
The uppermost 4-Kbyte sector of segment 0 (located in Flash module 0) is used
internally to store operation control parameters and protection information.
Note: The actual size of the Flash memory depends on the chosen device type.
Each sector can be separately write protected¹⁾, erased and programmed (in blocks of
128 Bytes). The complete Flash area can be read-protected. A user-defined password
sequence temporarily unlocks protected areas. The Flash modules combine 128-bit
read access with protected and efficient writing algorithms for programming and erasing.
Dynamic error correction provides extremely high read data security for all read access
operations. Access to different Flash modules can be executed in parallel.
For Flash parameters, please see Section 4.5.
Memory Content Protection
The contents of on-chip memories can be protected against soft errors (induced e.g. by
radiation) by activating the parity mechanism or the Error Correction Code (ECC).
The parity mechanism can detect a single-bit error and prevent the software from using
incorrect data or executing incorrect instructions.
The ECC mechanism can detect and automatically correct single-bit errors. This
supports the stable operation of the system.
It is strongly recommended to activate the ECC mechanism wherever possible because
this dramatically increases the robustness of an application against such soft errors.
1) To save control bits, sectors are clustered for protection purposes, they remain separate for
programming/erasing.
Data Sheet
53
V2.12, 2014-06