XC2385A_14 Datasheet, PDF (51/141 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

XC2385A, XC2387A
XC2000 Family / Base Line
Functional Description
3.1
Memory Subsystem and Organization
The memory space of the XC238xA is configured in the von Neumann architecture. In
this architecture all internal and external resources, including code memory, data
memory, registers and I/O ports, are organized in the same linear address space.
Table 8
XC238xA Memory Map ¹⁾
Address Area
Start Loc. End Loc.
IMB register space
FF’FF00_H
Reserved (Access trap) F0’0000_H
Reserved for EPSRAM E8’8000_H
Emulated PSRAM
E8’0000_H
Reserved for PSRAM E0’8000_H
Program SRAM
E0’0000_H
Reserved for Flash
CD’0000_H
Program Flash 3
CC’0000_H
Program Flash 2
C8’0000_H
Program Flash 1
C4’0000_H
Program Flash 0
C0’0000_H
External memory area 40’0000_H
Available Ext. IO area⁴⁾ 21’0000_H
Reserved
20’BC00_H
USIC alternate regs. 20’B000_H
MultiCAN alternate
regs.
20’8000_H
FF’FFFF_H
FF’FEFF_H
EF’FFFF_H
E8’7FFF_H
E7’FFFF_H
E0’7FFF_H
DF’FFFF_H
CC’FFFF_H
CB’FFFF_H
C7’FFFF_H
C3’FFFF_H
BF’FFFF_H
3F’FFFF_H
20’FFFF_H
20’BFFF_H
20’AFFF_H
Reserved
USIC registers
MultiCAN registers
External memory area
SFR area
Dual-Port RAM
Reserved for DPRAM
ESFR area
XSFR area
20’6000_H
20’4000_H
20’0000_H
01’0000_H
00’FE00_H
00’F600_H
00’F200_H
00’F000_H
00’E000_H
20’7FFF_H
20’5FFF_H
20’3FFF_H
1F’FFFF_H
00’FFFF_H
00’FDFF_H
00’F5FF_H
00’F1FF_H
00’EFFF_H
Area Size²⁾ Notes
256 Bytes –
<1 Mbyte Minus IMB registers
480 Kbytes Mirrors EPSRAM
32 Kbytes With Flash timing
480 Kbytes Mirrors PSRAM
32 Kbytes Maximum speed
<1.25 Mbytes –
64 Kbytes –
256 Kbytes –
256 Kbytes –
256 Kbytes ³⁾
8 Mbytes
–
< 2 Mbytes Minus USIC/CAN
17 Kbytes –
4 Kbytes
Accessed via EBC
12 Kbytes Accessed via EBC
8 Kbytes
8 Kbytes
16 Kbytes
< 2 Mbytes
0.5 Kbyte
2 Kbytes
1 Kbyte
0.5 Kbyte
4 Kbytes
–
Accessed via EBC
Accessed via EBC
Minus segment 0
–
–
–
–
–
Data Sheet
51
V2.12, 2014-06