SAB80C517 Datasheet, PDF (48/61 Pages) Siemens Semiconductor Group – 8-Bit CMOS Single-Chip Microcontroller

SAB 80C517/80C537
Notes for pages 44, 45 and 46:
1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed
on the V_OL of ALE and ports 1, 3, 4, 5 and 6. The noise is due to external bus capacitance
discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during
bus operation.
In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed
0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an
address latch with a schmitt- trigger strobe input.
2) Capacitive loading on ports 0 and 2 may cause the V_OH on ALE and PSEN to momentarily
fall below the 0.9 V_CC specification when the address lines are stabilizing.
3) Power down I_PD is measured with all output pins disconnected;
EA = RESET = V_CC; Port 0 = Port 7 = Port 8 = V_CC; XTAL1 = N.C.; XTAL2 = V_SS;
V_AGND= N.C.; V_AREF = V_CC; PE/SWD = OWE = V_SS.
4) I_CC (active mode) is measured with all output pins disconnected; XTAL2 driven with clock
signal according to the figure below; XTAL1 = N.C.;
EA = OWE = PE/SWD = V_CC; Port 0 = Port 7 = Port 8 = V_CC;
RESET = V_SS. I_CC would be slightly higher if a crystal oscillator is used.
5) I_CC (idle mode,) is measured with all output pins disconnected and with all peripherals
disabled; XTAL2 driven with clock signal according to the figure below; XTAL1 = N.C.;
RESET = OWE = V_CC; Port 0 = Port 7 = Port 8 = V_CC; EA = PE/SWD = V_SS.
I_CC (slow down mode) is measured with all output pins disconnected and with all peripherals
disabled; XTAL2 driven with clock signal according to the figure below; XTAL = N.C.;
Port 7 = Port 8 = V_CC; EA = PE/SWD = V_SS.
6) I_CC (max.) at other frequencies is given by: active mode: I_CC max = 3.1 _* f_OSC + 3.0
idle mode: I_CC max = 1.0 _* f_OSC + 3.0
Where f_OSC is the oscillator frequency in MHz. I_CC values are given in mA and measured at
V_CC = 5 V (see also notes 4 and 5).
7) The output impedance of the analog source must be low enough to assure full loading of the
sample capacitance (C_I) during load time (T_L). After charging of the internal capacitance (C_I)
in the load time (T_L) the analog input must be held constant for the rest of the sample time
(T_S).
8) The differential impedance R_D of the analog reference voltage source must be less than
1 kΩ at reference supply voltage.
9) Exceeding the limit values at one or more input channels will cause additional current which
is sinked sourced at these channels. This may also affect the accuracy of other channels
which are operated within the specification.
10) Only valid for not selected analog inputs.
11) No missing code.
Semiconductor Group
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