SAB80C517 Datasheet, PDF (38/61 Pages) Siemens Semiconductor Group – 8-Bit CMOS Single-Chip Microcontroller

SAB 80C517/80C537
Power Saving Modes
The SAB 80C517 provides – due to Siemens ACMOS technology – three modes in which
power consumption can be significantly reduced.
– The Slow Down Mode
The controller keeps up the full operating functionality, but is driven with the eighth part of its
normal operating frequency. Slowing down the frequency greatly reduces power
consumption.
– The Idle Mode
The CPU is gated off from the oscillator, but all peripherals are still supplied by the clock and
able to work.
– The Power Down Mode
Operation of the SAB 80C517 is stopped, the oscillator is turned off. This mode is used to
save the contents of the internal RAM with a very low standby current.
All of these modes are entered by software. Special function register PCON (power control
register, address is 87_H) is used to select one of these modes.
Hardware Enable for Power Saving Modes
A dedicated Pin (PE/SWD) of the SAB 80C517 allows to block the power saving modes. Since
this pin is mostly used in noise-critical application it is combined with an automatic start of the
Watchdog Timer (see there for further description).
PE/SWD = V_IH (logic high level):
Using of the power saving modes is not possible. The
instruction sequences used for entering of these modes
will not affect the normal operation of the device.
PE/SWD = V_IL (logic low level):
All power saving modes can be activated by software.
When left unconnected, Pin PE/SWD is pulled to high level
by a weak internal pullup. This is done to provide system
protection on default.
The logic-level applied to pin PE/SWD can be changed during program execution to allow or to
block the use of the power saving modes without any effect on the on-chip watchdog circuitry.
Power Down Mode
The power down mode is entered by two consecutive instructions directly following each other.
The first instruction has to set the flag PDE (power down enable) and must not set PDS (power
down set). The following instruction has to set the start bit PDS. Bits PDE and PDS will
automatically be cleared after having been set.
The instruction that sets bit PDS is the last instruction executed before going into power down
mode. The only exit from power down mode is a hardware reset.
The status of all output lines of the controller can be looked up in table 7.
Semiconductor Group
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