SAB80C517 Datasheet, PDF (39/61 Pages) Siemens Semiconductor Group – 8-Bit CMOS Single-Chip Microcontroller

SAB 80C517/80C537
Table 7
Status of External Pins During Idle and Power Down
Outputs
Last instruction executed from
internal code memory
Last instruction executed from
external code memory
Idle
Power down Idle
Power Down
ALE
PSEN
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
High
High
Data
Data/alternate
outputs
Data
Data/alternate
outputs
Data/alternate
outputs
Data/alternate
outputs
Data/alternate
outputs
Low
Low
Data
Data/last output
Data
Data/last output
Data/last output
Data/last output
Data/last output
High
High
Float
Data/alternate
outputs
Address
Data/alternate
outputs
Data/alternate
outputs
Data/alternate
outputs
Data/alternate
outputs
Low
Low
Float
Data/last output
Data
Data/last output
Data/last output
Data/last output
Data/last output
Idle Mode
During idle mode all peripherals of the SAB 80C517 are still supplied by the oscillator clock.
Thus the user has to take care which peripheral should continue to run and which has to be
stopped during Idle.
The procedure to enter the Idle mode is similar to entering the power down mode.
The two bits IDLE and IDLS must be set by to consecutive instructions to minimize the chance
of unintentional activating of the idle mode.
There are two ways to terminate the idle mode:
– The idle mode can be terminated by activating any enabled interrupt. This interrupt will be
serviced and normally the instruction to be executed following the RETI instruction will be
the one following the instruction that sets the bit IDLS.
– The other way to terminate the idle mode, is a hardware reset. Since the oscillator is still
running, the hardware reset must be held active only for two machine cycles for a complete
reset.
Normally the port pins hold the logical state they had at the time idle mode was activated. If
some pins are programmed to serve their alternate functions they still continue to output during
idle mode if the assigned function is on. The control signals ALE and PSEN hold at logic high
levels (see table 7).
Semiconductor Group
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