SAB80C517 Datasheet, PDF (32/61 Pages) Siemens Semiconductor Group – 8-Bit CMOS Single-Chip Microcontroller

SAB 80C517/80C537
Interrupt Structure
The SAB 80C517 has 14 interrupt vectors with the following vector addresses and request
flags.
Table 4
Interrupt Sources and Vectors
Source (Request Flags)
Vector Address
IE0
TF0
IE1
TF1
RI0/TI0
TF2 + EXF2
IADC
IEX2
IEX3
IEX4
IEX5
IEX6
RI1/TI1
CTF
0003_H
000B_H
0013_H
001B_H
0023_H
002B_H
0043_H
004B_H
0053_H
005B_H
0063_H
006B_H
0083_H
009B_H
Vector
External interrupt 0
Timer 0 overflow
External interrupt 1
Timer 1 overflow
Serial channel 0
Timer 2 overflow/ext. reload
A/D converter
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
Serial channel 1
Compare timer overflow
Each interrupt vector can be individually enabled/disabled. The response time to an interrupt
request is more than 3 machine cycles and less than 9 machine cycles.
External interrupts 0 and 1 can be activated by a low-level or a negative transition (selectable)
at their corresponding input pin, external interrupts 2 and 3 can be programmed for triggering
on a negative or a positive transition. The external interrupts 2 to 6 are combined with the
corresponding alternate functions compare (output) and capture (input) on port 1.
For programming of the priority levels the interrupt vectors are combined to pairs or triples.
Each pair or triple can be programmed individually to one of four priority levels by setting or
clearing one bit in special function register IP0 and one in IP1. Figure 9 shows the interrupt
request sources, the enabling and the priority level structure.
Semiconductor Group
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