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| PEB2255 Datasheet, PDF (324/374 Pages) Infineon Technologies AG – E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications | |||
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PEB 2255
FALC-LH V1.3
T1/J1 Registers
RABâ¦
Receive Message Aborted
The received frame was aborted from the transmitting station.
According to the HDLC protocol, this frame must be discarded by the
receiver station.
HA1...0â¦
High Byte Address Compare
Significant only if 2-byte address mode has been selected.
In operating modes which provide high byte address recognition, the
FALC®-LH compares the high byte of a 2-byte address with the
contents of two individually programmable registers (RAH1, RAH2)
and the fixed values FEH and FCH (broadcast address).
Dependent on the result of this comparison, the following bit
combinations are possible (SS7 support not active):
00⦠RAH2 has been recognized
01⦠Broadcast address has been recognized
10⦠RAH1 has been recognized C/R = 0 (bit 1)
11⦠RAH1 has been recognized C/R = 1 (bit 1)
Note: If RAH1, RAH2 contain identical values, a match is indicated
by â10â or â11â.
HFR â¦
HDLC Frame Format
0⦠A BOM frame was received.
1⦠A HDLC frame was received.
Note: Bits RSIS.7...2 and RSIS.0 are not valid with a BOM frame. This means, if HFR=0,
all other bits of RSIS have to be ignored
LA â¦
Low Byte Address Compare
Significant in HDLC modes only.
The low byte address of a 2-byte address field, or the single address
byte of a 1-byte address field is compared with two registers. (RAL1,
RAL2).
0⦠RAL2 has been recognized
1⦠RAL1 has been recognized
Data Sheet
324
2000-07
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