PEB2255 Datasheet, PDF (25/374 Pages) Infineon Technologies AG – E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PEB 2255
FALC-LH V1.3
Pin Descriptions
2.2
•
•
Table 1
Pin No.
42...48
41…38
35…28
25…22
49
52
Pin Definitions and Functions
Pin Definitions - Microprocessor Interface
Symbol
Input (I)
Output (O)
Supply (S)
Function
A0 … A6 I
Address Bus
These inputs interface to seven bits of the
system’s address bus to select one of the
internal registers for read or write.
D0…D3 I/O
D4…D11
D12..D15
Data Bus
Bidirectional tristate data lines which interface
to the system’s data bus. Their configuration is
controlled by the level of pin DBW:
8-bit mode (DBW = 0): D0 … D7 are active.
D8 … D15 are in high impedance and have to
be connected to V_DD or V_SS.
16-bit mode (DBW = 1): D0 … D15 are active.
In case of byte transfers, the active half of the
bus is determined by A0 and BHE/BLE and the
selected bus interface mode (via pin IM). The
unused half is in high impedance state.
ALE
I
CS
I
Address Latch Enable
A high on this line indicates an address on the
external address/data bus. The address
information provided on lines A0 … A6 is
internally latched with the falling edge of ALE.
This function allows the FALC^®-LH to be
connected to a multiplexed address/data bus
directly. In this case, pins A0 … A6 must be
connected to the Data Bus pins externally. In
case of demultiplexed mode this pin has to be
connected to V_DD or V_SS directly.
Chip Select
A low signal selects the FALC^®-LH for read
and write operations.
Data Sheet
25
2000-07