PEB2255 Datasheet, PDF (221/374 Pages) Infineon Technologies AG – E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PEB 2255
FALC-LH V1.3
E1 Registers
System Interface Control 1 (Read/Write)
Value after RESET: 00_H
7
SIC1 SRSC
RBS1 RBS0 SXSC
XBS1
0
XBS0
(3C)
SRSC…
Select Receive System Clock
0… expected frequency on pin SCLKR: 8.192 MHz
Calculation of delay time T (SCLKR cycles) depends on the
value X of the “Receive Counter Offset” register RC1/0 and of
the programming of RC0.RCOS.
Delay T is an even number in the range of 0 to 1022:
RCOS = 0: X = 5 − T/2 if 0 ≤ T ≤ 10
X = 517 − T/2 if 12 ≤ T ≤ 1022
Delay T is an odd number in the range of 1 to 1023:
RCOS = 1: X = 5 − (T − 1)/2 if 1 ≤ T ≤ 11
X = 517 − (T − 1)/2 if 13 ≤ T ≤ 1023
1… expected frequency on pin SCLKR: 2.048 MHz
Calculation of delay time T (SCLKR cycles) depends on the
value X of the “Receive Counter Offset” register RC1/0:
T = (260 − x/2) mod 256
RBS1...0…
Delay time T = time between beginning of time slot 0 at RDO
and the initial edge of SCLKR after SYPR goes active.
If this bit is set FMR1.IMOD must be set also and bit RC0.0
must be cleared.
Receive Buffer Size
00… buffer size : 2 frames
01… buffer size : 1 frame
10… buffer size : 92 bits
11… bypass of receive elastic store
Data Sheet
221
2000-07