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| PEB2255 Datasheet, PDF (268/374 Pages) Infineon Technologies AG – E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications | |||
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PEB 2255
FALC-LH V1.3
T1/J1 Registers
Common Configuration Register 3 (Read/Write)
Value after RESET: 00H
7
0
CCR3 PRE1 PRE0 EPT RADD
RCRC XCRC
(0A)
Unused bits have to be cleared.
PRE1...0â¦
Number of Preamble Repetitions
If preamble transmission is enabled, the preamble defined by register
PRE is transmitted:
00... 1 time
01... 2 times
10... 4 times
11... 8 times
EPTâ¦
Enable Preamble Transmission
This bit enables transmission of preamble. The preamble is started
after interframe timefill transmission has been stopped and a new
frame is to be transmitted. The preamble consists of an 8-bit pattern
repeated a number of times. The pattern is defined by register PRE,
the number of repetitions is selected by bits PRE0 and PRE1.
Note: The âShared Flagâ feature is not influenced by preamble transmission.
Zero bit insertion is disabled during preamble transmission.
RADDâ¦
Receive Address Pushed to RFIFO
If this bit is set, the received HDLC address information (1 or 2 bytes,
depending on the address mode selected via MODE.MDS0) is
pushed to RFIFO. See Chapter 8.1 on page 169 for detailed
description.
RCRCâ¦
Receive CRC ON/OFF
If this bit is set, the received CRC checksum is written to RFIFO
(CRC-ITU-T: 2 bytes). The checksum, consisting of the 2 last bytes in
the received frame, is followed in the RFIFO by the status information
byte (contents of register RSIS). The received CRC checksum is
additionally checked for correctness. If non-auto mode is selected,
the limits for âValid Frameâ check are modified (refer to RSIS.VFR and
to Chapter 8.1 on page 169).
Data Sheet
268
2000-07
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