PEB2255 Datasheet, PDF (284/374 Pages) Infineon Technologies AG – E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PEB 2255
FALC-LH V1.3
T1/J1 Registers
Transmit Control 1 (Read/Write)
Value after RESET: 00_H
7
0
XC1 XCOS
XTO5 XTO4 XTO3 XTO2 XTO1 XTO0 (21)
A write access to this address resets the transmit elastic buffer to its
basic starting position. Therefore, updating of the value should only
be done when the FALC^®-LH is initialized or when the buffer should
be centered. As a consequence a transmit slip occurs.
XCOS…
Transmit Clock Offset Shift
Valid only if SIC1.SXSC = 0
0… The delay T between the beginning of time slot 0 and the initial
edge of SCLKX (after SYPX goes active) is an even number in the
range of 0 to 1022 SCLKX cycles.
1… The delay T is an odd number in the range of 1 to 1023 SCLKX
cycles.
XTO5…XTO0… Transmit Time Slot Offset
Initial value loaded into the transmit bit counter at the trigger edge of
SCLKX when the synchronous pulse on port SYPX is active. Setting
of SIC1.SXSC enforces programming the offset values in the range
of 0 to 192 bits.
Receive Control 0 (Read/Write)
Value after RESET: 00_H
7
0
RC0 RCOS SICS CRCI XCRCI RDIS RCO2 RCO1 RCO0 (22)
RCOS…
Receive Clock Offset
Valid only if SIC1.SXSC = 0
0… The delay T between the beginning of time slot 0 and the initial
edge of SCLKR (after SYPX goes active) is an even number in the
range of 0 to 1022 SCLKX cycles.
1… The delay T is an odd number in the range of 1 to 1023 SCLKX
cycles.
Data Sheet
284
2000-07