PEB20534 Datasheet, PDF (312/439 Pages) Siemens Semiconductor Group – DMA Supported Serial Communication Controller with 4 Channels DSCC4

PEB 20534
PEF 20534
Detailed Register Description
Table 73 RTSA: Receive Time Slot Assignment Register
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
read/write
0000 0000_H
SCC0
SCC1
SCC2
SCC3
0120_H
01A0_H
0220_H
02A0_H
written by CPU, valid in HDLC clock mode 5 only
evaluated by DSCC4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Rx Time Slot Number
Rx Clock Shift
H0
RTSN(6:0)
00000
RCS(2:0)
A0
RTSN(6:0)
00000
RCS(2:0)
B0
RTSN(6:0)
00000
RCS(2:0)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Receive Time Slot Control
Receive Channel Capacity
H
000000
RCC(8:0)
A
000000
RCC(8:0)
B
000000
RCC(8:0)
Data Sheet
312
2000-05-30