PEB20534 Datasheet, PDF (223/439 Pages) Siemens Semiconductor Group – DMA Supported Serial Communication Controller with 4 Channels DSCC4

PEB 20534
PEF 20534
Detailed Register Description
of the additional locations 64-255 are used, nevertheless the DSCC4 responds to
configuration read/write cycles within the address range 00_H to FC_H.
These configuration registers are addressed only using the PCI Configuration read/write
cycles and using the IDSEL/DEVSEL handshake signals.
The PCI Configuration Space is also valid in de-multiplexed bus interface mode, i.e. pin
DEMUX connected to V_DD3. In this case only signal IDSEL is used to select the PCI
Configuration register set on read/write transactions.
The Base Address fields in the configuration space define the memory base addresses
and the corresponding address range the DSCC4 will respond to. The first Base
Address is the base address of the DSCC4’s on-chip register range (Global control
registers, SCC registers, LBI control registers, GPP Control registers, SSC registers).
The second Base Address is the base address of the memory mapped LBI address
space.
According to the PCI Specification, mapped address ranges are evaluated by writing all
ones to the base address registers and reading back the value. The number of leading
zeros determine the supported address range:
Table 40 PCI Base Address Ranges
Offset Register
Address
10_H
BAR1
Register Read Value
Supported Address Range
(after writing 0xFFFFFFFF_H)
0xFFFFF800_H
2 KByte
(DSCC4 on chip registers)
14_H
BAR2 0xFFFF0000_H
64 KByte
(Local bus address range mapped
to PCI (HOST) address space)
The status/command register (offset address 04_H) of the PCI Configuration Space
describes and determines the DSCC4 PCI system behavior and is described in details
in Table 41:
Data Sheet
223
2000-05-30