PEB20534 Datasheet, PDF (288/439 Pages) Siemens Semiconductor Group – DMA Supported Serial Communication Controller with 4 Channels DSCC4

PEB 20534
PEF 20534
Detailed Register Description
Table 68 CCR1: Channel Configuration Register 1
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
read/write
0000 0000_H
SCC0
SCC1
010C_H
018C_H
written by CPU
evaluated by DSCC4
SCC2
020C_H
SCC3
028C_H
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Output Control
H0 0
0
00
0
A0 0 0 0 0
00
0
0
B0 0 0 0 0
00
0
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Transmitter/Receiver Configuration
H
00000
A0 0 0 0 0 0 0
TOLEN
B0 0 0 0
0
00000000
Data Sheet
288
2000-05-30