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SPP07N60C3_09 Datasheet, PDF (3/15 Pages) Infineon Technologies AG – New revolutionary high voltage technology Ultra low gate charge Extreme dv/dt rated
SPP07N60C3
SPI07N60C3, SPA07N60C3
Electrical Characteristics, at Tj = 25 °C, unless otherwise specified
Parameter
Symbol
Conditions
Values
Unit
min. typ. max.
Characteristics
Transconductance
gfs
VDS≥2*ID*RDS(on)max,
-
6
-S
ID=4.6A
Input capacitance
Ciss
VGS=0V, VDS=25V,
- 790 - pF
Output capacitance
Coss
f=1MHz
- 260 -
Reverse transfer capacitance Crss
-
16
-
Effective output capacitance,4) Co(er) VGS=0V,
-
30
-
energy related
VDS=0V to 480V
Effective output capacitance,5) Co(tr)
-
55
-
time related
Turn-on delay time
Rise time
Turn-off delay time
Fall time
td(on)
VDD=380V, VGS=0/13V,
-
tr
ID=7.3A, RG=12Ω,
-
td(off)
Tj=125°C
-
tf
-
6
- ns
3.5
-
60 100
7
15
Gate Charge Characteristics
Gate to source charge
Qgs
VDD=480V, ID=7.3A
Gate to drain charge
Qgd
Gate charge total
Qg
VDD=480V, ID=7.3A,
VGS=0 to 10V
Gate plateau voltage
V(plateau) VDD=480V, ID=7.3A
-
3
- nC
-
9.2
-
-
21 27
-
5.5
-V
1Limited only by maximum temperature
2Repetitve avalanche causes additional power losses that can be calculated as PAV=EAR*f.
3Device on 40mm*40mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical without blown air.
4Co(er) is a fixed capacitance that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS.
5Co(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
6ISD<=ID, di/dt<=400A/us, VDClink=400V, Vpeak<VBR, DSS, Tj<Tj,max.
Identical low-side and high-side switch.
Rev. 3.2
Page 3
2009-11-27