HYS64D128320GU-6-A Datasheet, PDF (3/18 Pages) Infineon Technologies AG – 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules

HYS64/72D64000/128020GU-7/8-A
Unbuffered DDR-I SDRAM-Modules
Pin Definitions and Functions
A0 - A12
Address Inputs
BA0, BA1
Bank Selects
DQ0 - DQ63
Data Input/Output
CB0 - CB7
Check Bits (x72 organization only)
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Read/Write Input
CKE0 - CKE1
Clock Enable
DQS0 - DQS8
SDRAM low data strobes
CLK0 - CLK2,
SDRAM clock (positive lines)
CLK0 - CLK2
SDRAM clock (negative lines)
DM0 - DM8
DQS9 - DQS17
SDRAM low data mask/
high data strobes
note: S1 and CKE1 are used on two bank modules only
S0, S1
V_DD
V_SS
V_DDQ
V_DDID
V_REF
V_DDSPD
SCL
SDA
SA0 - SA2
NC
Chip Selects
Power (+ 2.5 V)
Ground
I/O Driver power supply
VDD Indentification flag
I/O reference supply
Serial EEPROM power supply
Serial bus clock
Serial bus data line
slave address select
no connect
Address Format
Density Organization
512 MB 64M x 64
512 MB 64M x 72
1024 MB 128M × 64
1024 MB 128M × 72
Memory
Banks
1
1
2
2
SDRAMs
64M x 8
64M x 8
64M x 8
64M x 8
# of
SDRAMs
8
9
16
18
# of row/bank/
columns bits
13/2/11
13/2/11
13/2/11
13/2/11
Refresh Period Interval
8k
64 ms 7.8 µs
8k
64 ms 7.8 µs
8k
64 ms 7.8 µs
8k
64 ms 7.8 µs
INFINEON Technologies
3
2002-09-10 (rev.0.81)