HYS64D128320GU-6-A Datasheet, PDF (14/18 Pages) Infineon Technologies AG – 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules

HYS64/72D64000/128020GU-7/8-A
Unbuffered DDR-I SDRAM-Modules
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5V ± 0.2V; V_DD = 2.5V ± 0.2V)
Symbol
Parameter
t_RFC
Auto-refresh to Active/Auto-refresh
command period
t_RCD Active to Read or Write delay
t_RP Precharge command period
t_RRD Active bank A to Active bank B command
t_WR Write recovery time
t_DAL
Auto precharge write recovery
+ precharge time
t_WTR
t_XSNR
t_XSRD
t_REFI
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic
Refresh Interval
512 Mbit based
DDR333
-6
Min Max
DDR266A
-7
Min Max
72
75
18
18
12
15
(twr/tck)
+ (trp/
tck)
1
75
200
20
20
15
15
(twr/tck)
+ (trp/
tck)
1
75
200
7.8
7.8
DDR200
-8
Min Max
80
20
20
15
15
Unit Notes
ns 1-4
ns 1-4
ns 1-4
ns 1-4
ns 1-4
t_CK 1-4,9
1
t_CK 1-4
80
ns 1-4
200
t_CK 1-4
7.8
µs 1-4, 8
1. Input slew rate >=1V/ns for DDR266 and = 1V/ns for DDR200.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is V_REF. CK/CK slew rate are >= 1.0 V/ns.
3. Inputs are not recognized as valid until V_REF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V_TT.
5. t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t_DQSS.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
10. These parameters guarantee device timing, but they are not necessarily tested on each device
11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew rate >1.0 V/
ns, measured between VOH(ac) and VOL(ac)
INFINEON Technologies
14
2002-09-10 (rev.0.81)