HYS64D128320GU-6-A Datasheet, PDF (11/18 Pages) Infineon Technologies AG – 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules

HYS64/72D64000/128020GU-7/8-A
Unbuffered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (PC1600)
Symbol
Parameter/Condition
512MB
x64
1bank
-8
512MB
x72
1bank
-8
1GB
x64
2bank
-8
1GB
x72
2bank
-8
Notes
Unit
MAX MAX MAX MAX
4
Operating Current: one bank; active / precharge; tRC = tRC MIN; tCK =
IDD0 tCK MIN; DQ, DM, and DQS inputs changing once per clock cycle;
1280 1440 1680 1890 mA
1
address and control inputs changing once every two clock cycles
IDD1
Operating Current: one bank; active/read/precharge; Burst = 4;
Refer to the following page for detailed test conditions.
1360 1530 1760 1980 mA 1, 3
IDD2P ^{Precharge Power-Down Standby Current: all banks idle; power-down}
96
mode; CKE <= VIL MAX; tCK = tCK MIN
108
192
216 mA
2
Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle;
IDD2F CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs
320
360
640
720 mA
2
changing once per clock cycle, VIN = VREF for DQ, DQS and DM.
Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle;
IDD2Q CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs
200
225
400
450 mA
2
stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM.
Active Power-Down Standby Current: one bank active; power-down
IDD3P mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and 128
144
256
288 mA
2
DM.
Active Standby Current: one bank active; active / precharge;CS >= VIH
MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and
IDD3N _{DQS inputs changing twice per clock cycle; address and control inputs} 400
450
800
900 mA
2
changing once per clock cycle
Operating Current: one bank active; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle; 50% of data
IDD4R
outputs changing on every clock edge; CL = 2 for DDR200, and
1320 1485 1720 1935 mA 1, 3
DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA
Operating Current: one bank active; Burst = 2; writes; continuous burst;
IDD4W
address and control inputs changing once per clock cycle; 50% of data
outputs changing on every clock edge; CL = 2 for DDR200, and
1280
1440
1680
1890 mA
1
DDR266A, CL=3 for DDR333; tCK = tCK MIN
IDD5
Auto-Refresh Current: tRC = tRFC MIN, distributed refresh
2320
2610
2720
3060 mA
1
IDD6 Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK MIN
40
45
80
90
mA
IDD7
Operating Current: four bank; four bank interleaving with BL=4;
Refer to the following page for detailed test conditions.
2800 3150 3200 3600 mA 1, 3
1. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component] for single bank modules (n: number of components per module bank)
n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank)
2. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component] for single bank modules (n: number of components per module bank)
2 * n * IDDx[component] for two bank modules (n: number of components per module bank)
3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
4. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C
INFINEON Technologies
11
2002-09-10 (rev.0.81)