HYE18P16161AC Datasheet, PDF (26/33 Pages) Infineon Technologies AG – 16M Asynchronous/Page CellularRAM

HYE18P16161AC(-/L)70/85
16M Asynch/Page CellularRAM
Functional Description
2.6
Deep Power Down Mode Entry/ Exit
To put the device in deep power down mode, it is required to comply with 2-step operation. At first, the DPD mode
bit (RCR.bit4) has be programmed to be enabled in the Refresh Configuration Register through SCR command.
When DPD entry is really required, ZZ pin must be asserted to low for longer than 10µs while CS1 sets to high as
shown in Figure 15. Between these 2 steps, any normal operations are permitted. Once the device enters into this
extreme low power mode, current consumption is cut down to less than 25µA.
Please note that 2 step operation for DPD entry is not designed to take place at a time when ZZ is held low. In
case of back-to-back operation to perform 2 steps, it is required to meet ZZ precharge time (t_ZPH).
All internal voltage generators inside the CelllularRAM are switched off and the internal self-refresh is stopped.
This means that all stored information will be lost in any time. The device will remain in DPD mode as long as ZZ
is held low. To exit the Deep Power Down mode, it is needed to simply bring ZZ to high voltage level. A guard time
of at least 150µs (t_R) has to be met where no commands beside DESELECT must be applied to re-enter standby
or idle mode.
Figure 16 Deep Power Down Entry/ Exit
(/ZZ high time is required between step 1 and 2)
(any normal operation is allowed in between)
CS1
t_CDZZ
ZZ
Step 1 (SCR)
RCR.bit4 should
be programmed
to enable DPD
t_ZPH
t_ZZMIN
Entering DPD
Step 2
/ZZ low for
longer than
tZZmin
Device in DPD
(maintaining)
t_R
Exiting DPD
Don't Care
Table 8 DPD/ ZZ Timing Table
Parameter
CS1 high setup time to ZZ low
ZZ precharge time
ZZ active for DPD entry
Recovery time from DPD exit
Symbol
t_CDZZ
t_ZPH
t_ZZMIN
t_R
70 & 85
Min.
Max.
5
–
5
–
10
–
150
–
Unit Notes
ns –
ns –
µs –
µs –
2.7
General AC Input/Output Reference Waveform
The input timings refer to a midlevel of V_DDQ/2 while as output timings refer to midlevel V_DDQ/2. The rising and
falling edges are 10 - 90% and < 2 ns.
Data Sheet
26
V2.0, 2003-12-16