HYE18P16161AC Datasheet, PDF (20/33 Pages) Infineon Technologies AG – 16M Asynchronous/Page CellularRAM

HYE18P16161AC(-/L)70/85
16M Asynch/Page CellularRAM
Functional Description
2.4
Asynchronous Read
[Disclaimer]
A20 input shown in timing diagrams is not used in 16Mbit CellularRAM. Should be “don’t care”.
The CellularRAM applies the standard asynchronous SRAM protocol to perform read and write accesses.
Reading from the device in asynchronous mode is accomplished by asserting the Chip Select (CS1) and Output
Enable (OE) signals to low while forcing Write Enable (WE) to high. If the Upper Byte (UB) control line is set active
low then the upper word of the addressed data is driven on the output lines, DQ15 to DQ8. If the Lower Byte (LB)
control line is set active low then the lower word of the addressed data is driven on the output lines, DQ7 to DQ0.
Figure 9
A20-A0
DQ15-DQ0
t_AA
t_OH
Previous Data
t_RC
ADDRESS
Data Valid
Not Valid
(note) A20 is “don’t care” in 16M CellularRAM
Asynchronous Read - Address Controlled (CS1 = OE = V_IL, WE = V_IH, UB and/or LB = V_IL,
ZZ = V_IH)
A20-A0
CS1
UB, LB
WE
OE
DQ15-DQ0
Don't Care
t_AA
t_CO
t_RC
ADDRESS
t_BA
t_BLZ
t_OE
t_OLZ
t_LZ
Figure 10 Asynchronous Read (WE = V_IH, ZZ = V_IH)
Data Valid
t_OH
t_CPH
t_BPH
t_HZ
t_BHZ
t_OHZ
(note) A20 is “don’t care” in 16M CellularRAM
Data Sheet
20
V2.0, 2003-12-16