HYE18P16161AC Datasheet, PDF (15/33 Pages) Infineon Technologies AG – 16M Asynchronous/Page CellularRAM

HYE18P16161AC(-/L)70/85
16M Asynch/Page CellularRAM
Functional Description
2.2
Access To The Control Register Map
[Disclaimer]
A20 input shown in timing diagrams is not used in 16Mbit CellularRAM. Should be “don’t care”.
Write-only access to the refresh control register is enabled by applying the SCR command and asserting the ZZ-
pin to low. Figure 5 shows the mapping of the address bus lines to the the refresh control register bits, whereas
in Figure 6 the access timing is illustrated.
A19 A18
00
A8 A7 A6 A5 A4 A3 A2 A1 A0 _{Address Bus}
0 PM TCSR DPD 0
PASR
Control Register
Control Register Select
A19
control reg
0
RCR
1
BCR
Page Mode Bit
A7
page mode
0
disabled (def.)
1
enabled
Deep Power Down Mode
A4
power down
0
enabled
1
disabled (def.)
A18....A8, A3:
reserved, must be set to '0'.
Temperature-Compensated
Self-Refresh
A6 A5 max. case temp.
11
+85°C (def.)
00
+70°C
01
+45°C
10
+15°C
Figure 5 Refresh Control Registers
Partial Array Self Refresh
A2 A1 A0 refreshed memory area
0 0 0 entire memory array (def.)
0 0 1 (reserved)
0 1 0 (reserved)
0 1 1 lower 1/2 of memory array
1 0 0 zero
1 0 1 upper 1/2 of memory array
1 1 0 (reserved)
1 1 1 (reserved)
A20-A0
CS1
UB, LB
WE
ZZ
DQ15-DQ0
Don't Care
RCR OPCODE
Open Latch
Initiate Control Register
Access
Figure 6 Control Register Write Access Protocol
Close Latch
(note) A20 is “don’t care” in 16M CellularRAM
Data Sheet
15
V2.0, 2003-12-16