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| HYE18P16161AC Datasheet, PDF (21/33 Pages) Infineon Technologies AG – 16M Asynchronous/Page CellularRAM | |||
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HYE18P16161AC(-/L)70/85
16M Asynch/Page CellularRAM
Functional Description
2.4.1 Page Read Mode
If activated by RCR.Bit7 page mode allows to toggle the four lower address bits (A3 to A0) to perform subsequent
random read accesses (max. 16-words by A3 - A0) at much faster speed than 1st read access. Page mode
operation supports only read access in CellularRAM. As soon as page mode is activated, CS1 low time restriction
(tCSL) applies. In case of CS1 staying low longer than tCSL limit, then it is alternative way to toggle non-page address
(A18 - A4) no later than tCSL,max. Therefore the usage of page mode is only recommended in systems which can
respect this limitation.
Please see also application note on Page 30.
A20-A4
A3-A0
CS1
UB, LB
WE
tRC
ADDRESS
tPC
ADDRESS
tAA
ADR
ADR
ADR
ADR
tCO
tCSL
tHZ
tBLZ
tBHZ
OE
DQ15-DQ0
tOLZ
tLZ
tOH
Data
Data
tPAA
Data
Data
Data
tOHZ
Don't Care
(note) A20 is âdonât careâ in 16M CellularRAM
Figure 11 Asynchronous Page Read Mode (ZZ = VIH)
Data Sheet
21
V2.0, 2003-12-16
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