HYS72D16500GR Datasheet, PDF (25/29 Pages) Infineon Technologies AG – Low Profile DDR SDRAM-Modules

HYS72D[16500/32501]GR-[7/8]-A
Low Profile Registered DDR SDRAM-Modules
Application Note
6
Application Note
Power Up and Power Management on DDR Registered DIMMs (according to JEDEC ballot JC-42.5 Item
1173)
184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and
to minimize power consumption during low power mode. One feature is externally controlled via a system-
generated RESET signal; the second is based on module detection of the input clocks. These enhancements
permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations
and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked
Loop) when the memory is in Self-Refresh mode.
The new RESET pin controls power dissipation on the module’s registers and ensures that CKE and other SDRAM
inputs are maintained at a valid ‘low’ level during power-up and self refresh. When RESET is at a low level, all the
register outputs are forced to a low level, and all differential register input receivers are powered down, resulting
in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as
an asynchronous signal according to the attached details. Using this function also permits the system and DIMM
clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs stay in Self Refresh
mode.
Table 13 RESET Truth Table
Register Inputs
Register
Outputs
RESET
CK
CK
Data in (D)
Data out (Q)
H
Rising
Falling
H
H
H
Rising
Falling
L
L
H
L or H
L or H
X
Qo
H
High Z
High Z
X
Illegal input
conditions
L
X or Hi-Z
X or Hi-Z
X or Hi-Z
L
X: Don’t care, Hi-Z: High Impedance, Qo: Data latched at the previous of CK rising and CK falling
As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are
maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low
maintains a high impedance state on the SDRAM DQ, DQS and DM outputs — where they will remain until
activated by a valid ‘read’ cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable.
The DDR PLL devices automatically detect clock activity above 20 MHz. When an input clock frequency of 20 MHz
or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating
frequency at which all specifications will be met is 95 MHz). If the clock input frequency drops below 20 MHz
(actual detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are
made High-Z, and the differential inputs are powered down — resulting in a total PLL current consumption of less
than 1 mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it
is tied inactive on the DIMM. This application note describes the required and optional system sequences
associated with the DDR Registered DIMM 'RESET' function. It is important to note that all references to CKE refer
to both CKE0 and CKE1 for a 2-rank DIMM. Because RESET applies to all DIMM register devices, it is therefore
not possible to uniquely control CKE to one physical DIMM rank through the use of the RESET pin.
Power-Up Sequence with RESET — Required
1. The system sets RESET at a valid low level.
This is the preferred default state during power-up. This input condition forces all register outputs to a low state
independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable low-level
at the DDR SDRAMs.
Data Sheet
25
Rev. 1.2, 2004-06
10292003-DNYO-BD9L