HYS72D16500GR Datasheet, PDF (21/29 Pages) Infineon Technologies AG – Low Profile DDR SDRAM-Modules

4
SPD Contents
HYS72D[16500/32501]GR-[7/8]-A
Low Profile Registered DDR SDRAM-Modules
SPD Contents
Table 12
Byte#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
SPD Codes
Description
Number of SPD Bytes
128
Total Bytes in Serial PD
256
Memory Type
DDR-SDRAM
Number of Row Addresses
12
Number of Column Addresses 10/11
Number of DIMM Ranks
1
Module Data Width
×72
Module Data Width (cont’d)
0
Module Interface Levels
SSTL_2.5
SDRAM Cycle Time at CL = 2.5 7 ns/8 ns
Access Time from Clock at
CL = 2.5
0.75 ns/0.8 ns
DIMM config
ECC
Refresh Rate/Type
Self-Refresh 15.6 ms
SDRAM Width, Primary
×8/×4
Error Checking SDRAM Data na
Witdh
Minimum Clock Delay for Back- t_CCD = 1 CLK
to-Back Random Column
Address
Burst Length Supported
2, 4 & 8
Number of SDRAM Ranks
4
Supported CAS Latencies
CAS latency = 2 & 2.5
CS Latencies
CS latency = 0
WE Latencies
Write latency = 1
SDRAM DIMM Module
Attributes
registered
SDRAM Device Attributes:
General
Concurrent Auto
Precharge
Min. Clock Cycle Time at CAS 7.5 ns/10 ns
Latency = 2
Access Time from Clock for
CL = 2
0.75 ns/0.8 ns
Minimum Clock Cycle Time for not supported
CL = 1.5
Access Time from Clock at
CL = 1.5
not supported
128MB
x72
1rank
-7
HEX.
80
08
07
0C
0A
01
48
00
04
70
75
128MB
x72
1rank
-8
HEX.
80
08
07
0C
0A
01
48
00
04
80
80
256MB
x72
1rank
-7
HEX.
80
08
07
0C
0B
01
48
00
04
70
75
256MB
x72
1rank
-8
HEX.
80
08
07
0C
0B
01
48
00
04
80
80
02
02
02
02
80
80
80
80
08
08
04
04
08
08
04
04
01
01
01
01
0E
0E
0E
0E
04
04
04
04
0C
0C
0C
0C
01
01
01
01
02
02
02
02
26
26
26
26
C0
C0
C0
C0
75
A0
75
A0
75
80
75
80
00
00
00
00
00
00
00
00
Data Sheet
21
Rev. 1.2, 2004-06
10292003-DNYO-BD9L